// Copyright (C) 1953-2022 NUDT
// Verilog module name - time_sensitive_switch 
// Version: V4.0.0.20221115
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:        
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module time_sensitive_switch
#(
    parameter NUM_GMAC = 4,  
    parameter NUM_XGMAC = 0,	
    parameter INDEX_HCP = 4,
    parameter PTP_RX_OFFSET_XGMII = 16'd51,//51.2ns
    parameter PTP_TX_OFFSET_XGMII = 16'd58, 
    parameter PTP_RX_OFFSET_GMII = 16'd192,
    parameter PTP_TX_OFFSET_GMII = 16'd72,    
    parameter CLK125MHz_PERIOD = {8'd8,41'h0},//8ns
    parameter CLK156p25MHz_PERIOD = {8'd6,41'h0cccccccccc},//6.4ns
	parameter SBM_PKT_WIDTH = 134,
	parameter MD_WIDTH = 300
)
(
     i_clk
    ,i_rst_n
    
    ,iv_hcp_mid                 //        
    //,i_local_cnt_rst            // local counter reset  
    ,i_tsn_or_tte 
    ,i_sync_step_mode    
	
	,iv_local_counter
	
    // port declaration
    ,i_gmii_rxclk
    ,i_gmii_rst_n        
    ,iv_gmii_rxd  
    ,i_gmii_rx_dv 
    ,i_gmii_rx_er 
    ,o_gmii_txclk        
    ,ov_gmii_txd  
    ,o_gmii_tx_en 
    ,o_gmii_tx_er     
    
    ,o_osm_req_rx_pulse 
    ,o_osm_resp_rx_pulse
    ,o_osm_req_tx_pulse 
    ,o_osm_resp_tx_pulse
    
    // configure interface 
    ,i_data_wr_hcp
    ,iv_data_hcp
    ,ov_data_hcp
    ,o_data_wr_hcp
    
    ,iv_localclk                    
    ,ov_tss_ver                           
    ,i_cyclestart
	,ov_schedule_period
    ,i_rc_rxenable                  
    ,i_st_rxenable                  
    
    ,o_tsmp_lookup_table_key_wr    
    ,ov_tsmp_lookup_table_key      
    ,iv_tsmp_lookup_table_outport  
    ,i_tsmp_lookup_table_outport_wr  
    
    ,iv_command         
    ,i_command_wr      
    ,ov_command_ack    
    ,o_command_ack_wr
    
    ,o_mirror_pkt_wr 
    ,ov_mirror_pkt   
    ,o_PTO0                  
    ,o_PTO1          
    ,o_PTO2          
    ,o_PTO3          
    
);
//I/O
input                   i_clk;                   //125Mhz
input                   i_rst_n;
//
input      [11:0]       iv_hcp_mid     ;
input                   i_tsn_or_tte   ;
input                   i_sync_step_mode;   
//input                   i_local_cnt_rst;

input       [39:0]		iv_local_counter;

input                   i_data_wr_hcp  ;
input      [8:0]        iv_data_hcp;                        
output     [8:0]        ov_data_hcp ;
output                  o_data_wr_hcp;
// gmii mac port interface
input      [NUM_GMAC-1:0]         i_gmii_rst_n    ;         

input      [NUM_GMAC-1:0]         i_gmii_rxclk    ;
input      [8*NUM_GMAC-1:0]       iv_gmii_rxd   ;
input      [NUM_GMAC-1:0]         i_gmii_rx_dv  ;
input      [NUM_GMAC-1:0]         i_gmii_rx_er  ;

output     [NUM_GMAC-1:0]         o_gmii_txclk;  
output     [8*NUM_GMAC-1:0]       ov_gmii_txd;
output     [NUM_GMAC-1:0]         o_gmii_tx_en;
output     [NUM_GMAC-1:0]         o_gmii_tx_er;

// pdelay_req/resp pulse, all mac included
output     [NUM_XGMAC + NUM_GMAC  -1:0]    o_osm_req_rx_pulse    ;
output     [NUM_XGMAC + NUM_GMAC  -1:0]    o_osm_resp_rx_pulse   ;
output     [NUM_XGMAC + NUM_GMAC  -1:0]    o_osm_req_tx_pulse    ;
output     [NUM_XGMAC + NUM_GMAC  -1:0]    o_osm_resp_tx_pulse   ;          
// 
input      [79:0]       iv_localclk                    ;
output     [31:0]       ov_tss_ver                    ;
output     [10:0]       ov_schedule_period;
input                   i_rc_rxenable                 ;
input                   i_st_rxenable                 ;
output                  o_tsmp_lookup_table_key_wr    ;
output     [47:0]       ov_tsmp_lookup_table_key      ;
input      [32:0]       iv_tsmp_lookup_table_outport  ;
input                   i_tsmp_lookup_table_outport_wr;
// csr interface
input      [63:0]       iv_command                   ;
input                   i_command_wr                 ;
output     [63:0]       ov_command_ack               ; 
output                  o_command_ack_wr             ;

input                   i_cyclestart                ;

output                  o_mirror_pkt_wr        ;
output     [8:0]        ov_mirror_pkt          ;
output                  o_PTO0                 ;
output                  o_PTO1                 ;
output                  o_PTO2                 ;
output                  o_PTO3                 ;

wire    [69*NUM_XGMAC-1:0]        wv_pkt_data_xgmac2nbi;
wire    [NUM_XGMAC-1:0]           wv_pkt_wr_xgmac2nbi;

// xgmac data
wire        [     NUM_XGMAC-1:0]   w_data_wr_nbo2xgmac   ;
wire        [69*NUM_XGMAC-1:0]   wv_data_nbo2xgmac     ;
wire        [     NUM_XGMAC-1:0]   w_data_ready_xgmac2nbo;

// gmac nbi
wire        [     (NUM_GMAC+NUM_XGMAC+1)-1:0]   w_wr_psc_cpe2psc     ;
wire        [     (NUM_GMAC+NUM_XGMAC+1)-1:0]   w_rd_psc_cpe2psc     ;
wire        [     (NUM_GMAC+NUM_XGMAC+1)-1:0]   w_wr_psc_psc2cpe     ;
wire        [  19*(NUM_GMAC+NUM_XGMAC+1)-1:0]   wv_addr_psc_psc2cpe  ;
wire        [  32*(NUM_GMAC+NUM_XGMAC+1)-1:0]   wv_rdata_psc_psc2cpe ;
wire        [     (NUM_GMAC+NUM_XGMAC+1)-1:0]   w_wr_pdg_cpe2pdg     ;
wire        [     (NUM_GMAC+NUM_XGMAC+1)-1:0]   w_rd_pdg_cpe2pdg     ;
wire        [     (NUM_GMAC+NUM_XGMAC+1)-1:0]   w_wr_pdg_pdg2cpe     ;
wire        [  19*(NUM_GMAC+NUM_XGMAC+1)-1:0]   wv_addr_pdg_pdg2cpe  ;
wire        [  32*(NUM_GMAC+NUM_XGMAC+1)-1:0]   wv_rdata_pdg_pdg2cpe ;

wire        [     (NUM_GMAC+NUM_XGMAC+1)-1:0]   w_bufid_wr_pcb2nip   ;
wire        [   9*(NUM_GMAC+NUM_XGMAC+1)-1:0]   wv_bufid_pcb2nip     ;
wire        [     (NUM_GMAC+NUM_XGMAC+1)-1:0]   w_bufid_ack_nip2pcb  ;

wire        [     (NUM_GMAC+NUM_XGMAC+1)-1:0]   w_md_wr_nip2flt      ;
wire        [ MD_WIDTH*(NUM_GMAC+NUM_XGMAC+1)-1:0]   wv_md_nip2flt        ;
wire        [     (NUM_GMAC+NUM_XGMAC+1)-1:0]   w_md_ack_flt2nip     ;


wire        [     (NUM_GMAC+NUM_XGMAC+1)-1:0]   w_wr_ctx_cpe2ctx     ;
wire        [     (NUM_GMAC+NUM_XGMAC+1)-1:0]   w_rd_ctx_cpe2ctx     ;


wire        [SBM_PKT_WIDTH*(NUM_GMAC+NUM_XGMAC+1)-1:0]   wv_pkt_data_nip2pcb  ;
wire        [     (NUM_GMAC+NUM_XGMAC+1)-1:0]   w_pkt_data_wr_nip2pcb;
wire        [  16*(NUM_GMAC+NUM_XGMAC+1)-1:0]   wv_pkt_addr_nip2pcb  ;
wire        [     (NUM_GMAC+NUM_XGMAC+1)-1:0]   w_pkt_ack_pcb2nip    ;

wire        [     (NUM_GMAC+NUM_XGMAC+1)-1:0]   w_pkt_rx_finish_nbi2sfc;
// gmac nos
wire        [     (NUM_GMAC+NUM_XGMAC+0)-1:0]   w_wr_cit2qgc        ;
wire        [     (NUM_GMAC+NUM_XGMAC+0)-1:0]   w_rd_cit2qgc        ;
wire        [     (NUM_GMAC+NUM_XGMAC+0)-1:0]   w_wr_qgc2cit        ;
wire        [  19*(NUM_GMAC+NUM_XGMAC+0)-1:0]   wv_addr_qgc2cit     ;
wire        [  32*(NUM_GMAC+NUM_XGMAC+0)-1:0]   wv_rdata_qgc2cit    ;
wire        [   9*(NUM_GMAC+NUM_XGMAC)-1:0]   wv_pkt_bufid_idc2nos   ;//lrl 0427//lyf0428
wire        [   3*(NUM_GMAC+NUM_XGMAC)-1:0]   wv_priority_idc2nos    ;//lrl 0427//lyf0428
wire        [     (NUM_GMAC+NUM_XGMAC)-1:0]   w_desp_wr_idc2nos       ;//lrl 0427//lyf0428
wire        [   9*(NUM_GMAC+NUM_XGMAC)-1:0]   wv_pkt_bufid_nos2nbo   ; // lrl 0427
wire        [     (NUM_GMAC+NUM_XGMAC)-1:0]   w_pkt_bufid_wr_nos2nbo ;// lrl 0427
wire        [     (NUM_GMAC+NUM_XGMAC)-1:0]   w_pkt_bufid_ack_nbo2nos;// lrl 0427

wire        [   9*(NUM_GMAC+NUM_XGMAC+1)-1:0]   wv_pkt_bufid_nop2pcb   ;
wire        [     (NUM_GMAC+NUM_XGMAC+1)-1:0]   w_pkt_bufid_wr_nop2pcb ;
wire        [     (NUM_GMAC+NUM_XGMAC+1)-1:0]   w_pkt_bufid_ack_pcb2nop;

wire        [  16*(NUM_GMAC+NUM_XGMAC+1)-1:0]   wv_pkt_raddr_nop2pcb   ;
wire        [     (NUM_GMAC+NUM_XGMAC+1)-1:0]   w_pkt_rd_nop2pcb       ;
wire        [     (NUM_GMAC+NUM_XGMAC+1)-1:0]   w_pkt_raddr_ack_pcb2nop;

wire        [SBM_PKT_WIDTH*(NUM_GMAC+NUM_XGMAC+1)-1:0]   wv_pkt_data_pcb2nop    ;
wire        [     (NUM_GMAC+NUM_XGMAC+1)-1:0]   w_pkt_data_wr_pcb2nop  ;

wire        [   9*NUM_GMAC-1:0]   wv_data_gmac2nbi        ;
wire        [     NUM_GMAC-1:0]   w_data_wr_gmac2nbi      ;

wire        [   9*NUM_GMAC-1:0]   wv_data_nbo2gmac        ;
wire        [     NUM_GMAC-1:0]   w_data_wr_nbo2gmac      ;
wire        [     NUM_GMAC-1:0]   w_data_ready_gmac2nbo   ;

wire        [     (NUM_GMAC+NUM_XGMAC+1 -1):0]   w_wr_ctx_ctx2cpe        ;
wire        [ (19*(NUM_GMAC+NUM_XGMAC+1)-1):0]   wv_addr_ctx_ctx2cpe     ;
wire        [ (32*(NUM_GMAC+NUM_XGMAC+1)-1):0]   wv_rdata_ctx_ctx2cpe    ;
assign w_wr_ctx_ctx2cpe     = {(   (NUM_GMAC+NUM_XGMAC+1)-1){1'b0}};
assign wv_addr_ctx_ctx2cpe  = {(19*(NUM_GMAC+NUM_XGMAC+1)-1){1'b0}};
assign wv_rdata_ctx_ctx2cpe = {(32*(NUM_GMAC+NUM_XGMAC+1)-1){1'b0}};

wire        [     (NUM_GMAC+NUM_XGMAC)-1:0]   w_wr_mih2mac     ;
wire        [     (NUM_GMAC+NUM_XGMAC)-1:0]   w_rd_mih2mac     ;

wire        [     (NUM_GMAC+NUM_XGMAC)-1:0]   w_wr_mac2mih        ;
wire        [  19*(NUM_GMAC+NUM_XGMAC)-1:0]   wv_addr_mac2mih     ;
wire        [  32*(NUM_GMAC+NUM_XGMAC)-1:0]   wv_rdata_mac2mih    ;
//*******************************
//              nip
//*******************************
wire                    w_hardware_initial_finish;
//wire       [10:0]       wv_schedule_period_grm2other           ;
wire       [10:0]       wv_time_slot_length_grm2other          ;

wire                    w_qbv_or_qch_grm2nop;   

// hcp 
wire       [8:0]        wv_bufid_pcb2nip_hcp;
wire                    w_bufid_wr_pcb2nip_hcp;
wire                    w_bufid_ack_hrp2nip_hcp;

wire       [299:0]      wv_md_cbi2sfc;
wire                    w_md_wr_cbi2sfc;
wire                    w_md_ack_sfc2cbi;

wire       [133:0]      wv_pkt_data_nip2pcb_hcp;
wire                    w_pkt_data_wr_nip2pcb_hcp;
wire       [15:0]       wv_pkt_addr_nip2pcb_hcp;
wire                    w_pkt_ack_pcb2nip_hcp;
//*******************************
//              flt
//*******************************
wire       [8:0]        wv_pkt_bufid_flt2pcb;    
wire                    w_pkt_bufid_wr_flt2pcb;  
wire       [5:0]        wv_pkt_bufid_cnt_flt2pcb;
// all ports 
wire       [9*NUM_GMAC-1:0]        wv_pkt_bufid_flt2nop  ;
wire       [3*NUM_GMAC-1:0]        wv_pkt_type_flt2nop   ;
wire                    w_pkt_bufid_wr_flt2nop;

//port  HCP
//*******************************
wire                    w_wr_cit2grm;
wire                    w_rd_cit2grm;   
                        
wire                    w_wr_cit2flt;
wire                    w_rd_cit2flt;
                        
wire                    w_wr_cit2pcb;
wire                    w_rd_cit2pcb;

wire                    w_wr_cit2trl;
wire                    w_rd_cit2trl;

wire                    w_wr_cit2idc;
wire                    w_rd_cit2idc;

wire                    w_wr_cit2ist;
wire                    w_rd_cit2ist;                  

wire                    w_wr_grm2cit         ;
wire         [18:0]     wv_addr_grm2cit      ;
wire                    w_addr_fixed_grm2cit ;
wire         [31:0]     wv_rdata_grm2cit     ;
                
wire                    w_wr_pcb2cit;
wire         [18:0]     wv_addr_pcb2cit;
wire                    w_addr_fixed_pcb2cit;
wire         [31:0]     wv_rdata_pcb2cit;
             
wire                    w_wr_flt2cit          ;
wire         [18:0]     wv_addr_flt2cit       ;
wire                    w_addr_fixed_flt2cit  ;
wire         [31:0]     wv_rdata_flt2cit      ;

wire                    w_wr_trl2cit          ;
wire         [18:0]     wv_addr_trl2cit       ;
wire                    w_addr_fixed_trl2cit  ;
wire         [31:0]     wv_rdata_trl2cit      ;

wire                    w_wr_idc2cit          ;
wire         [18:0]     wv_addr_idc2cit       ;
wire                    w_addr_fixed_idc2cit  ;
wire         [31:0]     wv_rdata_idc2cit      ;

wire                    w_wr_ist2cit          ;
wire         [18:0]     wv_addr_ist2cit       ;
wire                    w_addr_fixed_ist2cit  ;
wire         [31:0]     wv_rdata_ist2cit      ;
        
             
wire         [7:0]      wv_eth_data_cop2msl     ;
wire                    w_eth_data_wr_cop2msl   ;

(*MARK_DEBUG="ture"*)wire         [8:0]     wv_free_buf_fifo_rdusedw_pcb2cpa;
wire         [8:0]     wv_hpriority_be_police_threshold ;
wire         [8:0]     wv_rc_police_threshold_grm2nip   ;
wire         [8:0]     wv_lpriority_be_police_threshold ;

wire         [87:0]    wv_descriptor  ;
wire                   w_descriptor_wr;

wire       [8:0]        wv_pkt_bufid_idc2cbo;   
wire       [2:0]        wv_priority_idc2cbo ;     
wire       [5:0]        wv_inport_idc2cbo   ;
wire                    w_desp_wr_idc2cbo   ; 

wire         [8:0]     wv_bufid_idc2pcb   ;
wire                   w_bufid_wr_idc2pcb ;
wire                   w_bufid_ack_pcb2idc;

// global csr
wire [18:0] wv_addr_mih2other;
wire [31:0] wv_wdata_mih2other;



wire                   w_wr_mih2tau     ;
wire                   w_rd_mih2tau     ;
       
wire                   w_wr_tau2mih       ;
wire        [18:0]     wv_addr_tau2mih    ;
wire        [31:0]     wv_rdata_tau2mih   ;

assign o_gmii_txclk = i_gmii_rxclk;  
// HCP
share_buffer_input #(.inport(6'd4)) hcp_buffer_input_inst(
    .i_clk                           (i_clk),
    .i_rst_n                         (i_rst_n),
                                     
    .i_data_wr                      (i_data_wr_hcp),
    .iv_data                        (iv_data_hcp),
                                     
    .iv_addr                         (wv_addr_mih2other),                         
    .iv_wdata                        (wv_wdata_mih2other),                          
    .i_wr_psc                        (w_wr_psc_cpe2psc     [(NUM_XGMAC+NUM_GMAC)]),         
    .i_rd_psc                        (w_rd_psc_cpe2psc     [(NUM_XGMAC+NUM_GMAC)]),          
    .o_wr_psc                        (w_wr_psc_psc2cpe     [(NUM_XGMAC+NUM_GMAC)]),         
    .ov_addr_psc                     (wv_addr_psc_psc2cpe  [(NUM_XGMAC+NUM_GMAC)*19+:19]),      
    .ov_rdata_psc                    (wv_rdata_psc_psc2cpe [(NUM_XGMAC+NUM_GMAC)*32+:32]), 
    .i_wr_pdg                        (w_wr_pdg_cpe2pdg     [(NUM_XGMAC+NUM_GMAC)]),
    .i_rd_pdg                        (w_rd_pdg_cpe2pdg     [(NUM_XGMAC+NUM_GMAC)]),
    .o_wr_pdg                        (w_wr_pdg_pdg2cpe     [(NUM_XGMAC+NUM_GMAC)]),                     
    .ov_addr_pdg                     (wv_addr_pdg_pdg2cpe  [(NUM_XGMAC+NUM_GMAC)*19+:19]),
    .ov_rdata_pdg                    (wv_rdata_pdg_pdg2cpe [(NUM_XGMAC+NUM_GMAC)*32+:32]),                 
                                     
    .i_pkt_bufid_wr                  (w_bufid_wr_pcb2nip   [(NUM_XGMAC+NUM_GMAC)]  ),
    .iv_pkt_bufid                    (wv_bufid_pcb2nip     [(NUM_XGMAC+NUM_GMAC)*9+:9]    ),
    .o_pkt_bufid_ack                 (w_bufid_ack_nip2pcb  [(NUM_XGMAC+NUM_GMAC)] ),
                                     
    .o_md_wr                         (w_md_wr_nip2flt      [(NUM_XGMAC+NUM_GMAC)]),
    .ov_md                           (wv_md_nip2flt        [(NUM_XGMAC+NUM_GMAC)*MD_WIDTH+:MD_WIDTH]),
    .i_md_ack                        (w_md_ack_flt2nip     [(NUM_XGMAC+NUM_GMAC)]),
                                     
    .ov_pkt                          (wv_pkt_data_nip2pcb  [(NUM_XGMAC+NUM_GMAC)*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
    .o_pkt_wr                        (w_pkt_data_wr_nip2pcb[(NUM_XGMAC+NUM_GMAC)]),
    .ov_pkt_bufadd                   (wv_pkt_addr_nip2pcb  [(NUM_XGMAC+NUM_GMAC)*16+:16]),
    .i_pkt_ack                       (w_pkt_ack_pcb2nip    [(NUM_XGMAC+NUM_GMAC)]),
    
    .i_rc_rxenable                   (i_rc_rxenable                 ),
    .i_st_rxenable                   (i_st_rxenable                 ),
    
    .i_hardware_initial_finish       (w_hardware_initial_finish     ),
    .o_pkt_rx_finish                 (w_pkt_rx_finish_nbi2sfc[NUM_GMAC+NUM_XGMAC]     ),
    .iv_rc_police_threshold           (wv_rc_police_threshold_grm2nip         ),
    .iv_hpriority_be_police_threshold (wv_hpriority_be_police_threshold ),
    .iv_lpriority_be_police_threshold (wv_lpriority_be_police_threshold),             
    .iv_free_bufid_fifo_rdusedw      (wv_free_buf_fifo_rdusedw_pcb2cpa)
);

// instance of 16*1G-MAC
generate 
genvar i;
for(i=0; i<=NUM_GMAC-1; i = i+1) begin: GMAC_GROUP
    media_access_control #(.osm_id(i),.local_module_id(i+1),.ptp_rx_offset_gmii(PTP_RX_OFFSET_GMII),.ptp_tx_offset_gmii(PTP_TX_OFFSET_GMII),.clk_period(CLK125MHz_PERIOD)) media_access_control
    (                    
    .i_gmii_clk        (i_gmii_rxclk[i]            ),                   
    .i_gmii_rst_n      (i_gmii_rst_n[i]            ),                                               
    .i_clk             (i_clk                      ),
    .i_rst_n           (i_rst_n                    ),
    
    .iv_addr           (wv_addr_mih2other),      
    .iv_wdata          (wv_wdata_mih2other),                    
    .i_wr              (w_wr_mih2mac    [i]       ),
    .i_rd              (w_rd_mih2mac    [i]       ),
    .o_wr              (w_wr_mac2mih    [i]       ),
    .ov_addr           (wv_addr_mac2mih [i*19+:19]),
    .ov_rdata          (wv_rdata_mac2mih[i*32+:32]),                
    
    .iv_hcp_mid        (iv_hcp_mid                 ),                                                    
    //.i_local_cnt_rst   (i_local_cnt_rst            ),                 
    //.iv_local_counter  (wv_local_counter_hcp2tss),                                                                
    .i_port_type       (1'b0                       ),                
    .i_tsn_or_tte      (i_tsn_or_tte               ),
    .i_sync_step_mode  (i_sync_step_mode           ), 

	.iv_local_counter  (iv_local_counter),
                                                                     
    .i_gmii_rx_dv      (i_gmii_rx_dv[i]            ),                
    .i_gmii_rx_er      (i_gmii_rx_er[i]            ),
    .iv_gmii_rxd       (iv_gmii_rxd [i*8+:8]       ),
    .o_gmii_tx_en      (o_gmii_tx_en[i]            ),
    .o_gmii_tx_er      (o_gmii_tx_er[i]            ),
    .ov_gmii_txd       (ov_gmii_txd [i*8+:8]       ),
                                                   
    .i_data_wr         (w_data_wr_nbo2gmac   [i]           ),
    .iv_data           (wv_data_nbo2gmac     [i*9+:9]),
    .o_data_ready      (w_data_ready_gmac2nbo[i]           ),

    .o_data_wr         (w_data_wr_gmac2nbi   [i]           ),
    .ov_data           (wv_data_gmac2nbi     [i*9+:9]),
    
    .o_osm_req_rx_pulse (o_osm_req_rx_pulse[i]     ),
    .o_osm_resp_rx_pulse(o_osm_resp_rx_pulse[i]    ),
    .o_osm_req_tx_pulse (o_osm_req_tx_pulse[i]     ),
    .o_osm_resp_tx_pulse(o_osm_resp_tx_pulse[i]    ),
    
    //.i_sync_generate_pulse(i_sync_generate_pulse),
    .o_sync_pulse_portrx  (o_sync_pulse_portrx)
);

share_buffer_input #(.inport(i)) network_buffer_input_1g(
        .i_clk                           (i_clk),
        .i_rst_n                         (i_rst_n),
                                            
        .i_data_wr                       (w_data_wr_gmac2nbi[i]),
        .iv_data                         (wv_data_gmac2nbi  [i*9+:9]  ),
                                         
        .iv_addr                         (wv_addr_mih2other),                         
        .iv_wdata                        (wv_wdata_mih2other),                          
        .i_wr_psc                        (w_wr_psc_cpe2psc     [i]),         
        .i_rd_psc                        (w_rd_psc_cpe2psc     [i]),          
        .o_wr_psc                        (w_wr_psc_psc2cpe     [i]),         
        .ov_addr_psc                     (wv_addr_psc_psc2cpe  [i*19+:19]),      
        .ov_rdata_psc                    (wv_rdata_psc_psc2cpe [i*32+:32]), 
        .i_wr_pdg                        (w_wr_pdg_cpe2pdg     [i]),                        
        .i_rd_pdg                        (w_rd_pdg_cpe2pdg     [i]),
        .o_wr_pdg                        (w_wr_pdg_pdg2cpe     [i]),                     
        .ov_addr_pdg                     (wv_addr_pdg_pdg2cpe  [i*19+:19]),                  
        .ov_rdata_pdg                    (wv_rdata_pdg_pdg2cpe [i*32+:32]),                 
                                         
        .i_pkt_bufid_wr                  (w_bufid_wr_pcb2nip   [i]  ),
        .iv_pkt_bufid                    (wv_bufid_pcb2nip     [i*9+:9]    ),
        .o_pkt_bufid_ack                 (w_bufid_ack_nip2pcb  [i] ),
                                         
        .o_md_wr                         (w_md_wr_nip2flt      [i]),
        .ov_md                           (wv_md_nip2flt        [i*MD_WIDTH+:MD_WIDTH]),
        .i_md_ack                        (w_md_ack_flt2nip     [i]),
                                         
        .ov_pkt                          (wv_pkt_data_nip2pcb  [i*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
        .o_pkt_wr                        (w_pkt_data_wr_nip2pcb[i]),
        .ov_pkt_bufadd                   (wv_pkt_addr_nip2pcb  [i*16+:16]),
        .i_pkt_ack                       (w_pkt_ack_pcb2nip    [i]),
        
        .i_rc_rxenable                   (i_rc_rxenable                 ),
        .i_st_rxenable                   (i_st_rxenable                 ),
        
        .i_hardware_initial_finish       (w_hardware_initial_finish     ),
        .o_pkt_rx_finish                 (w_pkt_rx_finish_nbi2sfc[i]     ),
        .iv_rc_police_threshold          (wv_rc_police_threshold_grm2nip         ),
        .iv_hpriority_be_police_threshold(wv_hpriority_be_police_threshold ),
        .iv_lpriority_be_police_threshold(wv_lpriority_be_police_threshold),             
        .iv_free_bufid_fifo_rdusedw      (wv_free_buf_fifo_rdusedw_pcb2cpa)
    );


    network_outport_schedule 
    #(
      .clk_period(CLK125MHz_PERIOD)
    )    
    network_outport_schedule_1g(
        .i_clk              (i_clk  ) ,  
        .i_rst_n            (i_rst_n) ,
                                      
        .iv_addr            (wv_addr_mih2other      ) ,         
        .iv_wdata           (wv_wdata_mih2other     ) ,
        .i_wr_qgc           (w_wr_cit2qgc        [i]),
        .i_rd_qgc           (w_rd_cit2qgc        [i]),
        .o_wr_qgc           (w_wr_qgc2cit        [i]),
        .ov_addr_qgc        (wv_addr_qgc2cit     [i*19+:19]),
        .ov_rdata_qgc       (wv_rdata_qgc2cit    [i*32+:32]),         
           
        .i_cyclestart       (i_cyclestart                 ),              
        .iv_time_slot_length(wv_time_slot_length_grm2other ),              
        .iv_schedule_period (ov_schedule_period  ),              
        .i_qbv_or_qch       (w_qbv_or_qch_grm2nop),                                                
        
        .iv_pkt_bufid       (wv_pkt_bufid_idc2nos   [i*9+:9]),       
        .iv_priority        (wv_priority_idc2nos    [i*3+:3]),       
        .i_desp_wr          (w_desp_wr_idc2nos      [i]),          
                                        
        .ov_pkt_bufid       (wv_pkt_bufid_nos2nbo   [i*9+:9]),
        .o_pkt_bufid_wr     (w_pkt_bufid_wr_nos2nbo [i]),
        .i_pkt_bufid_ack    (w_pkt_bufid_ack_nbo2nos[i]),
                           
        .ov_osc_state       ()          
    );


    network_buffer_output #(.frame_gap(5'd2)) network_buffer_output_1g(
        .i_clk              (i_clk  ) ,  
        .i_rst_n            (i_rst_n) ,
        
        .iv_pkt_bufid       (wv_pkt_bufid_nos2nbo   [i*9+:9]),                              
        .i_pkt_bufid_wr     (w_pkt_bufid_wr_nos2nbo [i]),
        .o_pkt_bufid_ack    (w_pkt_bufid_ack_nbo2nos[i]),
        
        .ov_pkt_bufid       (wv_pkt_bufid_nop2pcb   [i*9+:9]),                   
        .o_pkt_bufid_wr     (w_pkt_bufid_wr_nop2pcb [i]),                
        .i_pkt_bufid_ack    (w_pkt_bufid_ack_pcb2nop[i]),         
                                                                    
        .ov_pkt_raddr       (wv_pkt_raddr_nop2pcb   [i*16+:16]),            
        .o_pkt_rd           (w_pkt_rd_nop2pcb       [i]),                    
        .i_pkt_raddr_ack    (w_pkt_raddr_ack_pcb2nop[i]),                
                                                                         
        .iv_pkt_data        (wv_pkt_data_pcb2nop    [i*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),             
        .i_pkt_data_wr      (w_pkt_data_wr_pcb2nop  [i]),            
                                                                   
        .ov_data            (wv_data_nbo2gmac        [i*9+:9]),                    
        .o_data_wr          (w_data_wr_nbo2gmac      [i]),   
        .i_data_ready       (w_data_ready_gmac2nbo   [i])                                                               
    );
end
endgenerate
    
stream_forwarding_control 
#(
    .NUM_GMAC(NUM_GMAC)
   ,.NUM_XGMAC(NUM_XGMAC)
)
stream_forwarding_control_inst(
.i_clk                      (i_clk),
.i_rst_n                    (i_rst_n),
        
.iv_addr                    (wv_addr_mih2other      ),
.iv_wdata                   (wv_wdata_mih2other     ),
.i_wr                       (w_wr_cit2flt         ),
.i_rd                       (w_rd_cit2flt         ),                     
.o_wr                       (w_wr_flt2cit         ),
.ov_addr                    (wv_addr_flt2cit      ),
.ov_rdata                   (wv_rdata_flt2cit     )   ,
        
.i_cyclestart               (i_cyclestart),
.iv_inject_period           (ov_schedule_period),

.i_pkt_rx_finish            (w_pkt_rx_finish_nbi2sfc),

.iv_md_p0                   (wv_md_nip2flt   [0*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p0                 (w_md_wr_nip2flt [0]),
.o_md_ack_p0                (w_md_ack_flt2nip[0]),
                
.iv_md_p1                   (wv_md_nip2flt[1*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p1                 (w_md_wr_nip2flt[1]),
.o_md_ack_p1                (w_md_ack_flt2nip[1]),
                
.iv_md_p2                   (wv_md_nip2flt[2*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p2                 (w_md_wr_nip2flt[2]),
.o_md_ack_p2                (w_md_ack_flt2nip[2]),
        
.iv_md_p3                   (wv_md_nip2flt[3*MD_WIDTH+:MD_WIDTH]   ),
.i_md_wr_p3                 (w_md_wr_nip2flt[3] ),
.o_md_ack_p3                (w_md_ack_flt2nip[3]),

.iv_md_p4                   (wv_md_nip2flt   [4*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p4                 (w_md_wr_nip2flt [4]),
.o_md_ack_p4                (w_md_ack_flt2nip[4]),
                                       
.iv_md_p5                   ({MD_WIDTH{1'b0}}  ),   //(wv_md_nip2flt   [5*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p5                 (1'b0 ), //(w_md_wr_nip2flt [5]),
.o_md_ack_p5                (),      //(w_md_ack_flt2nip[5]),
 
.iv_md_p6                   ({MD_WIDTH{1'b0}}  ),   //(wv_md_nip2flt   [6*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p6                 (1'b0 ), //(w_md_wr_nip2flt [6]),
.o_md_ack_p6                (),      //(w_md_ack_flt2nip[6]),
 
.iv_md_p7                   ({MD_WIDTH{1'b0}}  ),   //(wv_md_nip2flt   [7*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p7                 (1'b0 ), //(w_md_wr_nip2flt [7]),
.o_md_ack_p7                (),      //(w_md_ack_flt2nip[7]),
 
.iv_md_p8                   ({MD_WIDTH{1'b0}}),   //(wv_md_nip2flt   [8*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p8                 (1'b0 ), //(w_md_wr_nip2flt [8]),
.o_md_ack_p8                (),      //(w_md_ack_flt2nip[8]),
 
.iv_md_p9                   ({MD_WIDTH{1'b0}}),   //(wv_md_nip2flt   [9*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p9                 (1'b0 ), //(w_md_wr_nip2flt [9]),
.o_md_ack_p9                (),      //(w_md_ack_flt2nip[9]),
 
.iv_md_p10                  ({MD_WIDTH{1'b0}}),   //(wv_md_nip2flt   [10*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p10                (1'b0 ), //(w_md_wr_nip2flt [10]),
.o_md_ack_p10               (),      //(w_md_ack_flt2nip[10]),
 
.iv_md_p11                  ({MD_WIDTH{1'b0}}),   //(wv_md_nip2flt   [11*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p11                (1'b0 ), //(w_md_wr_nip2flt [11]),
.o_md_ack_p11               (),      //(w_md_ack_flt2nip[11]),
 
.iv_md_p12                  ({MD_WIDTH{1'b0}}),   //(wv_md_nip2flt   [12*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p12                (1'b0 ), //(w_md_wr_nip2flt [12]),
.o_md_ack_p12               (),      //(w_md_ack_flt2nip[12]),
 
.iv_md_p13                  ({MD_WIDTH{1'b0}}),   //(wv_md_nip2flt   [13*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p13                (1'b0 ), //(w_md_wr_nip2flt [13]),
.o_md_ack_p13               (),      //(w_md_ack_flt2nip[13]),
 
.iv_md_p14                  ({MD_WIDTH{1'b0}}),   //(wv_md_nip2flt   [14*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p14                (1'b0 ), //(w_md_wr_nip2flt [14]),
.o_md_ack_p14               (),      //(w_md_ack_flt2nip[14]),
 
.iv_md_p15                  ({MD_WIDTH{1'b0}}),   //(wv_md_nip2flt   [15*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p15                (1'b0 ), //(w_md_wr_nip2flt [15]),
.o_md_ack_p15               (),      //(w_md_ack_flt2nip[15]),
 
.iv_md_p16                  ({MD_WIDTH{1'b0}}),   //(wv_md_nip2flt   [16*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p16                (1'b0 ), //(w_md_wr_nip2flt [16]),
.o_md_ack_p16               (),      //(w_md_ack_flt2nip[16]),
 
.iv_md_p17                  ({MD_WIDTH{1'b0}}),   //(wv_md_nip2flt   [17*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p17                (1'b0 ), //(w_md_wr_nip2flt [17]),
.o_md_ack_p17               (),      //(w_md_ack_flt2nip[17]),
 
.iv_md_p18                  ({MD_WIDTH{1'b0}}),   //(wv_md_nip2flt   [18*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p18                (1'b0 ), //(w_md_wr_nip2flt [18]),
.o_md_ack_p18               (),      //(w_md_ack_flt2nip[18]),
 
.iv_md_p19                  ({MD_WIDTH{1'b0}}),   //(wv_md_nip2flt   [19*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p19                (1'b0 ), //(w_md_wr_nip2flt [19]),
.o_md_ack_p19               (),      //(w_md_ack_flt2nip[19]),
 
.iv_md_p20                  ({MD_WIDTH{1'b0}}),   //(wv_md_nip2flt   [20*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p20                (1'b0 ), //(w_md_wr_nip2flt [20]),
.o_md_ack_p20               (),      //(w_md_ack_flt2nip[20]),
 
.iv_md_p21                  ({MD_WIDTH{1'b0}}),   //  (wv_md_nip2flt   [21*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p21                (1'b0 ), //  (w_md_wr_nip2flt [21]),
.o_md_ack_p21               (),      //  (w_md_ack_flt2nip[21]),
 
.iv_md_p22                  ({MD_WIDTH{1'b0}}),//wv_md_nip2flt   [22*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p22                (  1'b0),//w_md_wr_nip2flt [22]),
.o_md_ack_p22               (  ),//w_md_ack_flt2nip[22]),
 
.iv_md_p23                  ({MD_WIDTH{1'b0}}),//(wv_md_nip2flt   [23*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p23                (  1'b0),//(w_md_wr_nip2flt [23]),
.o_md_ack_p23               (  ),//(w_md_ack_flt2nip[23]),
 
.iv_md_p24                  ({MD_WIDTH{1'b0}}),//(wv_md_nip2flt   [24*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p24                (  1'b0),//(w_md_wr_nip2flt [24]),
.o_md_ack_p24               (  ),//(w_md_ack_flt2nip[24]),
 
.iv_md_p25                  ({MD_WIDTH{1'b0}}),//(wv_md_nip2flt   [25*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p25                (  1'b0),//(w_md_wr_nip2flt [25]),
.o_md_ack_p25               (  ),//(w_md_ack_flt2nip[25]),
 
.iv_md_p26                  ({MD_WIDTH{1'b0}}),//(wv_md_nip2flt   [26*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p26                (  1'b0),//(w_md_wr_nip2flt [26]),
.o_md_ack_p26               (  ),//(w_md_ack_flt2nip[26]),
 
.iv_md_p27                  ({MD_WIDTH{1'b0}}),//(wv_md_nip2flt   [27*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p27                (  1'b0),//(w_md_wr_nip2flt [27]),
.o_md_ack_p27               (  ),//(w_md_ack_flt2nip[27]),
 
.iv_md_p28                  ({MD_WIDTH{1'b0}}),//(wv_md_nip2flt   [28*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p28                (  1'b0),//(w_md_wr_nip2flt [28]),
.o_md_ack_p28               (  ),//(w_md_ack_flt2nip[28]),
 
.iv_md_p29                  ({MD_WIDTH{1'b0}}),//(wv_md_nip2flt   [29*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p29                (  1'b0),//(w_md_wr_nip2flt [29]),
.o_md_ack_p29               (  ),//(w_md_ack_flt2nip[29]),
 
.iv_md_p30                  ({MD_WIDTH{1'b0}}),//(wv_md_nip2flt   [30*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p30                (  1'b0),//(w_md_wr_nip2flt [30]),
.o_md_ack_p30               (  ),//(w_md_ack_flt2nip[30]),
 
.iv_md_p31                  ({MD_WIDTH{1'b0}}),//(wv_md_nip2flt   [31*MD_WIDTH+:MD_WIDTH]),
.i_md_wr_p31                (  1'b0),//(w_md_wr_nip2flt [31]),
.o_md_ack_p31               (  ),//(w_md_ack_flt2nip[31]),
 
.iv_md_p32                  ({MD_WIDTH{1'b0}}),//   (wv_md_cbi2sfc     ),
.i_md_wr_p32                (  1'b0),//   (w_md_wr_cbi2sfc   ),
.o_md_ack_p32               ( ),//   (w_md_ack_sfc2cbi  ),

.o_tsmp_lookup_table_key_wr     (o_tsmp_lookup_table_key_wr    ),
.ov_tsmp_lookup_table_key       (ov_tsmp_lookup_table_key      ),
.iv_tsmp_lookup_table_outport   (iv_tsmp_lookup_table_outport  ),
.i_tsmp_lookup_table_outport_wr (i_tsmp_lookup_table_outport_wr), 

.ov_desp             (wv_descriptor  ),
.o_desp_wr           (w_descriptor_wr),
        
.ov_pkt_bufid               (wv_pkt_bufid_flt2pcb    ),
.o_pkt_bufid_wr             (w_pkt_bufid_wr_flt2pcb  ),
.ov_pkt_bufid_cnt           (wv_pkt_bufid_cnt_flt2pcb) 
);

shared_buffer_management shared_buffer_management_inst(
.i_clk                   (i_clk               ),
.i_rst_n                 (i_rst_n             ), 

.o_hardware_initial_finish(w_hardware_initial_finish),

.iv_addr                 (wv_addr_mih2other     ),                         
.iv_wdata                (wv_wdata_mih2other    ),                            
.i_wr                    (w_wr_cit2pcb        ),                        
.i_rd                    (w_rd_cit2pcb        ), 
.o_wr                    (w_wr_pcb2cit        ),                     
.ov_addr                 (wv_addr_pcb2cit     ),                  
.ov_rdata                (wv_rdata_pcb2cit    ),  
    
.iv_pkt_p0               (wv_pkt_data_nip2pcb  [0*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
.i_pkt_wr_p0             (w_pkt_data_wr_nip2pcb[0]),
.iv_pkt_wr_bufadd_p0     (wv_pkt_addr_nip2pcb  [0*16+:16]),
.o_pkt_wr_ack_p0         (w_pkt_ack_pcb2nip    [0]),
                         
.iv_pkt_p1               (wv_pkt_data_nip2pcb  [1*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
.i_pkt_wr_p1             (w_pkt_data_wr_nip2pcb[1]),
.iv_pkt_wr_bufadd_p1     (wv_pkt_addr_nip2pcb  [1*16+:16]),
.o_pkt_wr_ack_p1         (w_pkt_ack_pcb2nip    [1]),
                         
.iv_pkt_p2               (wv_pkt_data_nip2pcb  [2*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
.i_pkt_wr_p2             (w_pkt_data_wr_nip2pcb[2]),
.iv_pkt_wr_bufadd_p2     (wv_pkt_addr_nip2pcb  [2*16+:16]),
.o_pkt_wr_ack_p2         (w_pkt_ack_pcb2nip    [2]),

.iv_pkt_p3               (wv_pkt_data_nip2pcb  [3*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
.i_pkt_wr_p3             (w_pkt_data_wr_nip2pcb[3]),
.iv_pkt_wr_bufadd_p3     (wv_pkt_addr_nip2pcb  [3*16+:16]),
.o_pkt_wr_ack_p3         (w_pkt_ack_pcb2nip    [3]),

.iv_pkt_p4               (wv_pkt_data_nip2pcb  [4*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
.i_pkt_wr_p4             (w_pkt_data_wr_nip2pcb[4]),
.iv_pkt_wr_bufadd_p4     (wv_pkt_addr_nip2pcb  [4*16+:16]),
.o_pkt_wr_ack_p4         (w_pkt_ack_pcb2nip    [4]),

.iv_pkt_p5               ({SBM_PKT_WIDTH{1'b0}}),//(wv_pkt_data_nip2pcb  [5*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
.i_pkt_wr_p5             (1'b0),//(w_pkt_data_wr_nip2pcb[5]),
.iv_pkt_wr_bufadd_p5     ('b0),//(wv_pkt_addr_nip2pcb  [5*16+:16]),
.o_pkt_wr_ack_p5         (), //(w_pkt_ack_pcb2nip    [5]),
    
.iv_pkt_p6               ({SBM_PKT_WIDTH{1'b0}}),//(wv_pkt_data_nip2pcb  [6*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
.i_pkt_wr_p6             (1'b0),//(w_pkt_data_wr_nip2pcb[6]),
.iv_pkt_wr_bufadd_p6     ('b0),//(wv_pkt_addr_nip2pcb  [6*16+:16]),
.o_pkt_wr_ack_p6         (), //(w_pkt_ack_pcb2nip    [6]),
    
.iv_pkt_p7               ({SBM_PKT_WIDTH{1'b0}}),//(wv_pkt_data_nip2pcb  [7*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
.i_pkt_wr_p7             (1'b0),//(w_pkt_data_wr_nip2pcb[7]),
.iv_pkt_wr_bufadd_p7     ('b0),//(wv_pkt_addr_nip2pcb  [7*16+:16]),
.o_pkt_wr_ack_p7         (), //(w_pkt_ack_pcb2nip    [7]),

.iv_pkt_p8               ({SBM_PKT_WIDTH{1'b0}}),//(wv_pkt_data_nip2pcb  [8*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
.i_pkt_wr_p8             (1'b0),//(w_pkt_data_wr_nip2pcb[8]),
.iv_pkt_wr_bufadd_p8     ('b0),//(wv_pkt_addr_nip2pcb  [8*16+:16]),
.o_pkt_wr_ack_p8         (), //(w_pkt_ack_pcb2nip    [8]),

.iv_pkt_p9               ({SBM_PKT_WIDTH{1'b0}}),//(wv_pkt_data_nip2pcb  [9*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
.i_pkt_wr_p9             (1'b0),//(w_pkt_data_wr_nip2pcb[9]),
.iv_pkt_wr_bufadd_p9     ('b0),//(wv_pkt_addr_nip2pcb  [9*16+:16]),
.o_pkt_wr_ack_p9         (), //(w_pkt_ack_pcb2nip    [9]),
//
//.iv_pkt_p10               (wv_pkt_data_nip2pcb  [10*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.i_pkt_wr_p10             (w_pkt_data_wr_nip2pcb[10]),
//.iv_pkt_wr_bufadd_p10     (wv_pkt_addr_nip2pcb  [10*13+:13]),
//.o_pkt_wr_ack_p10         (w_pkt_ack_pcb2nip    [10]),
//
//.iv_pkt_p11               (wv_pkt_data_nip2pcb  [11*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.i_pkt_wr_p11             (w_pkt_data_wr_nip2pcb[11]),
//.iv_pkt_wr_bufadd_p11     (wv_pkt_addr_nip2pcb  [11*13+:13]),
//.o_pkt_wr_ack_p11         (w_pkt_ack_pcb2nip    [11]),
//
//.iv_pkt_p12               (wv_pkt_data_nip2pcb  [12*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.i_pkt_wr_p12             (w_pkt_data_wr_nip2pcb[12]),
//.iv_pkt_wr_bufadd_p12     (wv_pkt_addr_nip2pcb  [12*13+:13]),
//.o_pkt_wr_ack_p12         (w_pkt_ack_pcb2nip    [12]),
//
//.iv_pkt_p13               (wv_pkt_data_nip2pcb  [13*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.i_pkt_wr_p13             (w_pkt_data_wr_nip2pcb[13]),
//.iv_pkt_wr_bufadd_p13     (wv_pkt_addr_nip2pcb  [13*13+:13]),
//.o_pkt_wr_ack_p13         (w_pkt_ack_pcb2nip    [13]),
//
//.iv_pkt_p14               (wv_pkt_data_nip2pcb  [14*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.i_pkt_wr_p14             (w_pkt_data_wr_nip2pcb[14]),
//.iv_pkt_wr_bufadd_p14     (wv_pkt_addr_nip2pcb  [14*13+:13]),
//.o_pkt_wr_ack_p14         (w_pkt_ack_pcb2nip    [14]),
//
//.iv_pkt_p15               (wv_pkt_data_nip2pcb  [15*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.i_pkt_wr_p15             (w_pkt_data_wr_nip2pcb[15]),
//.iv_pkt_wr_bufadd_p15     (wv_pkt_addr_nip2pcb  [15*13+:13]),
//.o_pkt_wr_ack_p15         (w_pkt_ack_pcb2nip    [15]),
//
//.iv_pkt_p16               (wv_pkt_data_nip2pcb  [16*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.i_pkt_wr_p16             (w_pkt_data_wr_nip2pcb[16]),
//.iv_pkt_wr_bufadd_p16     (wv_pkt_addr_nip2pcb  [16*13+:13]),
//.o_pkt_wr_ack_p16         (w_pkt_ack_pcb2nip    [16]),
//
//.iv_pkt_p17               (wv_pkt_data_nip2pcb  [17*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.i_pkt_wr_p17             (w_pkt_data_wr_nip2pcb[17]),
//.iv_pkt_wr_bufadd_p17     (wv_pkt_addr_nip2pcb  [17*13+:13]),
//.o_pkt_wr_ack_p17         (w_pkt_ack_pcb2nip    [17]),
//
//.iv_pkt_p18               (wv_pkt_data_nip2pcb  [18*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.i_pkt_wr_p18             (w_pkt_data_wr_nip2pcb[18]),
//.iv_pkt_wr_bufadd_p18     (wv_pkt_addr_nip2pcb  [18*13+:13]),
//.o_pkt_wr_ack_p18         (w_pkt_ack_pcb2nip    [18]),
//
//.iv_pkt_p19               (wv_pkt_data_nip2pcb  [19*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.i_pkt_wr_p19             (w_pkt_data_wr_nip2pcb[19]),
//.iv_pkt_wr_bufadd_p19     (wv_pkt_addr_nip2pcb  [19*13+:13]),
//.o_pkt_wr_ack_p19         (w_pkt_ack_pcb2nip    [19]),
//
//.iv_pkt_p20               (wv_pkt_data_nip2pcb  [20*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.i_pkt_wr_p20             (w_pkt_data_wr_nip2pcb[20]           ),
//.iv_pkt_wr_bufadd_p20     (wv_pkt_addr_nip2pcb  [20*13+:13]    ),
//.o_pkt_wr_ack_p20         (w_pkt_ack_pcb2nip    [20]           ),
//
//.iv_pkt_p21               (wv_pkt_data_nip2pcb  [21*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.i_pkt_wr_p21             (w_pkt_data_wr_nip2pcb[21]),
//.iv_pkt_wr_bufadd_p21     (wv_pkt_addr_nip2pcb  [21*13+:13]),
//.o_pkt_wr_ack_p21         (w_pkt_ack_pcb2nip    [21]),
//
//.iv_pkt_p22               (wv_pkt_data_nip2pcb  [22*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.i_pkt_wr_p22             (w_pkt_data_wr_nip2pcb[22]),
//.iv_pkt_wr_bufadd_p22     (wv_pkt_addr_nip2pcb  [22*13+:13]),
//.o_pkt_wr_ack_p22         (w_pkt_ack_pcb2nip    [22]),
//
//.iv_pkt_p23               (wv_pkt_data_nip2pcb  [23*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.i_pkt_wr_p23             (w_pkt_data_wr_nip2pcb[23]),
//.iv_pkt_wr_bufadd_p23     (wv_pkt_addr_nip2pcb  [23*13+:13]),
//.o_pkt_wr_ack_p23         (w_pkt_ack_pcb2nip    [23]),
//
//.iv_pkt_p24               (wv_pkt_data_nip2pcb  [24*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.i_pkt_wr_p24             (w_pkt_data_wr_nip2pcb[24]),
//.iv_pkt_wr_bufadd_p24     (wv_pkt_addr_nip2pcb  [24*13+:13]),
//.o_pkt_wr_ack_p24         (w_pkt_ack_pcb2nip    [24]),
//
//.iv_pkt_p25               (wv_pkt_data_nip2pcb  [25*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.i_pkt_wr_p25             (w_pkt_data_wr_nip2pcb[25]),
//.iv_pkt_wr_bufadd_p25     (wv_pkt_addr_nip2pcb  [25*13+:13]),
//.o_pkt_wr_ack_p25         (w_pkt_ack_pcb2nip    [25]),
//
//.iv_pkt_p26               (wv_pkt_data_nip2pcb  [26*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.i_pkt_wr_p26             (w_pkt_data_wr_nip2pcb[26]),
//.iv_pkt_wr_bufadd_p26     (wv_pkt_addr_nip2pcb  [26*13+:13]),
//.o_pkt_wr_ack_p26         (w_pkt_ack_pcb2nip    [26]),
//
//.iv_pkt_p27               (wv_pkt_data_nip2pcb  [27*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.i_pkt_wr_p27             (w_pkt_data_wr_nip2pcb[27]),
//.iv_pkt_wr_bufadd_p27     (wv_pkt_addr_nip2pcb  [27*13+:13]),
//.o_pkt_wr_ack_p27         (w_pkt_ack_pcb2nip    [27]),
//
//.iv_pkt_p28               (wv_pkt_data_nip2pcb  [28*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.i_pkt_wr_p28             (w_pkt_data_wr_nip2pcb[28]),
//.iv_pkt_wr_bufadd_p28     (wv_pkt_addr_nip2pcb  [28*13+:13]),
//.o_pkt_wr_ack_p28         (w_pkt_ack_pcb2nip    [28]),
//
//.iv_pkt_p29               (wv_pkt_data_nip2pcb  [29*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.i_pkt_wr_p29             (w_pkt_data_wr_nip2pcb[29]),
//.iv_pkt_wr_bufadd_p29     (wv_pkt_addr_nip2pcb  [29*13+:13]),
//.o_pkt_wr_ack_p29         (w_pkt_ack_pcb2nip    [29]),
//
//.iv_pkt_p30               (wv_pkt_data_nip2pcb  [30*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.i_pkt_wr_p30             (w_pkt_data_wr_nip2pcb[30]),
//.iv_pkt_wr_bufadd_p30     (wv_pkt_addr_nip2pcb  [30*13+:13]),
//.o_pkt_wr_ack_p30         (w_pkt_ack_pcb2nip    [30]),
//
//.iv_pkt_p31               (wv_pkt_data_nip2pcb  [31*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.i_pkt_wr_p31             (w_pkt_data_wr_nip2pcb[31]),
//.iv_pkt_wr_bufadd_p31     (wv_pkt_addr_nip2pcb  [31*13+:13]),
//.o_pkt_wr_ack_p31         (w_pkt_ack_pcb2nip    [31]),

//.iv_pkt_hcp               (wv_pkt_data_nip2pcb_hcp  ),
//.i_pkt_wr_hcp             (w_pkt_data_wr_nip2pcb_hcp),
//.iv_pkt_wr_bufadd_hcp     (wv_pkt_addr_nip2pcb_hcp  ),
//.o_pkt_wr_ack_hcp         (w_pkt_ack_pcb2nip_hcp    ),

///

.iv_pkt_rd_bufadd_p0     (wv_pkt_raddr_nop2pcb   [0*16+:16]),
.i_pkt_rd_p0             (w_pkt_rd_nop2pcb       [0]),
.o_pkt_rd_ack_p0         (w_pkt_raddr_ack_pcb2nop[0]),
.ov_pkt_p0               (wv_pkt_data_pcb2nop    [0*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
.o_pkt_wr_p0             (w_pkt_data_wr_pcb2nop  [0]),

.iv_pkt_rd_bufadd_p1     (wv_pkt_raddr_nop2pcb   [1*16+:16]),
.i_pkt_rd_p1             (w_pkt_rd_nop2pcb       [1]),
.o_pkt_rd_ack_p1         (w_pkt_raddr_ack_pcb2nop[1]),
.ov_pkt_p1               (wv_pkt_data_pcb2nop    [1*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
.o_pkt_wr_p1             (w_pkt_data_wr_pcb2nop  [1]),

.iv_pkt_rd_bufadd_p2     (wv_pkt_raddr_nop2pcb   [2*16+:16]),
.i_pkt_rd_p2             (w_pkt_rd_nop2pcb       [2]),
.o_pkt_rd_ack_p2         (w_pkt_raddr_ack_pcb2nop[2]),
.ov_pkt_p2               (wv_pkt_data_pcb2nop    [2*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
.o_pkt_wr_p2             (w_pkt_data_wr_pcb2nop  [2]),

.iv_pkt_rd_bufadd_p3     (wv_pkt_raddr_nop2pcb   [3*16+:16]),
.i_pkt_rd_p3             (w_pkt_rd_nop2pcb       [3]),
.o_pkt_rd_ack_p3         (w_pkt_raddr_ack_pcb2nop[3]),
.ov_pkt_p3               (wv_pkt_data_pcb2nop    [3*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
.o_pkt_wr_p3             (w_pkt_data_wr_pcb2nop  [3]),

.iv_pkt_rd_bufadd_p4     (wv_pkt_raddr_nop2pcb   [4*16+:16]),
.i_pkt_rd_p4             (w_pkt_rd_nop2pcb       [4]),
.o_pkt_rd_ack_p4         (w_pkt_raddr_ack_pcb2nop[4]),
.ov_pkt_p4               (wv_pkt_data_pcb2nop    [4*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
.o_pkt_wr_p4             (w_pkt_data_wr_pcb2nop  [4]),

.iv_pkt_rd_bufadd_p5     (0),//(wv_pkt_raddr_nop2pcb   [5*16+:16]),
.i_pkt_rd_p5             (0),//(w_pkt_rd_nop2pcb       [5]),
.o_pkt_rd_ack_p5         (), //(w_pkt_raddr_ack_pcb2nop[5]),
.ov_pkt_p5               (), //(wv_pkt_data_pcb2nop    [5*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
.o_pkt_wr_p5             (), //(w_pkt_data_wr_pcb2nop  [5]),

.iv_pkt_rd_bufadd_p6     (0),//(wv_pkt_raddr_nop2pcb   [6*16+:16]),
.i_pkt_rd_p6             (0),//(w_pkt_rd_nop2pcb       [6]),
.o_pkt_rd_ack_p6         (), //(w_pkt_raddr_ack_pcb2nop[6]),
.ov_pkt_p6               (), //(wv_pkt_data_pcb2nop    [6*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
.o_pkt_wr_p6             (), //(w_pkt_data_wr_pcb2nop  [6]),

.iv_pkt_rd_bufadd_p7     (0),//(wv_pkt_raddr_nop2pcb   [7*16+:16]),
.i_pkt_rd_p7             (0),//(w_pkt_rd_nop2pcb       [7]),
.o_pkt_rd_ack_p7         (), //(w_pkt_raddr_ack_pcb2nop[7]),
.ov_pkt_p7               (), //(wv_pkt_data_pcb2nop    [7*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
.o_pkt_wr_p7             (), //(w_pkt_data_wr_pcb2nop  [7]),

.iv_pkt_rd_bufadd_p8     (0),//(wv_pkt_raddr_nop2pcb   [8*16+:16]),
.i_pkt_rd_p8             (0),//(w_pkt_rd_nop2pcb       [8]),
.o_pkt_rd_ack_p8         (), //(w_pkt_raddr_ack_pcb2nop[8]),
.ov_pkt_p8               (), //(wv_pkt_data_pcb2nop    [8*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
.o_pkt_wr_p8             (), //(w_pkt_data_wr_pcb2nop  [8]),

.iv_pkt_rd_bufadd_p9     (0),//(wv_pkt_raddr_nop2pcb   [9*16+:16]),
.i_pkt_rd_p9             (0),//(w_pkt_rd_nop2pcb       [9]),
.o_pkt_rd_ack_p9         (), //(w_pkt_raddr_ack_pcb2nop[9]),
.ov_pkt_p9               (), //(wv_pkt_data_pcb2nop    [9*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
.o_pkt_wr_p9             (), //(w_pkt_data_wr_pcb2nop  [9]),
//
//.iv_pkt_rd_bufadd_p10     (wv_pkt_raddr_nop2pcb   [10*13+:13]),
//.i_pkt_rd_p10             (w_pkt_rd_nop2pcb       [10]),
//.o_pkt_rd_ack_p10         (w_pkt_raddr_ack_pcb2nop[10]),
//.ov_pkt_p10               (wv_pkt_data_pcb2nop    [10*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.o_pkt_wr_p10             (w_pkt_data_wr_pcb2nop  [10]),
//
//.iv_pkt_rd_bufadd_p11     (wv_pkt_raddr_nop2pcb   [11*13+:13]),
//.i_pkt_rd_p11             (w_pkt_rd_nop2pcb       [11]),
//.o_pkt_rd_ack_p11         (w_pkt_raddr_ack_pcb2nop[11]),
//.ov_pkt_p11               (wv_pkt_data_pcb2nop    [11*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.o_pkt_wr_p11             (w_pkt_data_wr_pcb2nop  [11]),
//
//.iv_pkt_rd_bufadd_p12     (wv_pkt_raddr_nop2pcb   [12*13+:13]),
//.i_pkt_rd_p12             (w_pkt_rd_nop2pcb       [12]),
//.o_pkt_rd_ack_p12         (w_pkt_raddr_ack_pcb2nop[12]),
//.ov_pkt_p12               (wv_pkt_data_pcb2nop    [12*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.o_pkt_wr_p12             (w_pkt_data_wr_pcb2nop  [12]),
//
//.iv_pkt_rd_bufadd_p13     (wv_pkt_raddr_nop2pcb   [13*13+:13]),
//.i_pkt_rd_p13             (w_pkt_rd_nop2pcb       [13]),
//.o_pkt_rd_ack_p13         (w_pkt_raddr_ack_pcb2nop[13]),
//.ov_pkt_p13               (wv_pkt_data_pcb2nop    [13*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.o_pkt_wr_p13             (w_pkt_data_wr_pcb2nop  [13]),
//
//.iv_pkt_rd_bufadd_p14     (wv_pkt_raddr_nop2pcb   [14*13+:13]),
//.i_pkt_rd_p14             (w_pkt_rd_nop2pcb       [14]),
//.o_pkt_rd_ack_p14         (w_pkt_raddr_ack_pcb2nop[14]),
//.ov_pkt_p14               (wv_pkt_data_pcb2nop    [14*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.o_pkt_wr_p14             (w_pkt_data_wr_pcb2nop  [14]),
//
//.iv_pkt_rd_bufadd_p15     (wv_pkt_raddr_nop2pcb   [15*13+:13]),
//.i_pkt_rd_p15             (w_pkt_rd_nop2pcb       [15]),
//.o_pkt_rd_ack_p15         (w_pkt_raddr_ack_pcb2nop[15]),
//.ov_pkt_p15               (wv_pkt_data_pcb2nop    [15*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.o_pkt_wr_p15             (w_pkt_data_wr_pcb2nop  [15]),
//
//.iv_pkt_rd_bufadd_p16     (wv_pkt_raddr_nop2pcb   [16*13+:13]),
//.i_pkt_rd_p16             (w_pkt_rd_nop2pcb       [16]),
//.o_pkt_rd_ack_p16         (w_pkt_raddr_ack_pcb2nop[16]),
//.ov_pkt_p16               (wv_pkt_data_pcb2nop    [16*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.o_pkt_wr_p16             (w_pkt_data_wr_pcb2nop  [16]),
//
//.iv_pkt_rd_bufadd_p17     (wv_pkt_raddr_nop2pcb   [17*13+:13]),
//.i_pkt_rd_p17             (w_pkt_rd_nop2pcb       [17]),
//.o_pkt_rd_ack_p17         (w_pkt_raddr_ack_pcb2nop[17]),
//.ov_pkt_p17               (wv_pkt_data_pcb2nop    [17*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.o_pkt_wr_p17             (w_pkt_data_wr_pcb2nop  [17]),
//
//.iv_pkt_rd_bufadd_p18     (wv_pkt_raddr_nop2pcb   [18*13+:13]),
//.i_pkt_rd_p18             (w_pkt_rd_nop2pcb       [18]),
//.o_pkt_rd_ack_p18         (w_pkt_raddr_ack_pcb2nop[18]),
//.ov_pkt_p18               (wv_pkt_data_pcb2nop    [18*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.o_pkt_wr_p18             (w_pkt_data_wr_pcb2nop  [18]),
//
//.iv_pkt_rd_bufadd_p19     (wv_pkt_raddr_nop2pcb   [19*13+:13]),
//.i_pkt_rd_p19             (w_pkt_rd_nop2pcb       [19]),
//.o_pkt_rd_ack_p19         (w_pkt_raddr_ack_pcb2nop[19]),
//.ov_pkt_p19               (wv_pkt_data_pcb2nop    [19*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.o_pkt_wr_p19             (w_pkt_data_wr_pcb2nop  [19]),
//
//.iv_pkt_rd_bufadd_p20     (wv_pkt_raddr_nop2pcb   [20*13+:13]),
//.i_pkt_rd_p20             (w_pkt_rd_nop2pcb       [20]),
//.o_pkt_rd_ack_p20         (w_pkt_raddr_ack_pcb2nop[20]),
//.ov_pkt_p20               (wv_pkt_data_pcb2nop    [20*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
//.o_pkt_wr_p20             (w_pkt_data_wr_pcb2nop  [20]),
//
///
.   ov_pkt_bufid_p0       (wv_bufid_pcb2nip   [0*9+:9]),
. o_pkt_bufid_wr_p0       (w_bufid_wr_pcb2nip [0]     ),
.i_pkt_bufid_ack_p0       (w_bufid_ack_nip2pcb[0]     ),
                         
.   ov_pkt_bufid_p1        (wv_bufid_pcb2nip   [1 *9+:9]),
. o_pkt_bufid_wr_p1        (w_bufid_wr_pcb2nip [1 ]     ),
.i_pkt_bufid_ack_p1        (w_bufid_ack_nip2pcb[1 ]     ),
                                                  
.   ov_pkt_bufid_p2        (wv_bufid_pcb2nip   [2 *9+:9]),
. o_pkt_bufid_wr_p2        (w_bufid_wr_pcb2nip [2 ]     ),
.i_pkt_bufid_ack_p2        (w_bufid_ack_nip2pcb[2 ]     ),
                                                  
.   ov_pkt_bufid_p3        (wv_bufid_pcb2nip   [3 *9+:9]),
. o_pkt_bufid_wr_p3        (w_bufid_wr_pcb2nip [3 ]     ),
.i_pkt_bufid_ack_p3        (w_bufid_ack_nip2pcb[3 ]     ),
                                                  
.   ov_pkt_bufid_p4        (wv_bufid_pcb2nip   [4 *9+:9]),
. o_pkt_bufid_wr_p4        (w_bufid_wr_pcb2nip [4 ]     ),
.i_pkt_bufid_ack_p4        (w_bufid_ack_nip2pcb[4 ]     ),
                                                  
.   ov_pkt_bufid_p5        (    ),//(wv_bufid_pcb2nip   [5 *9+:9]),
. o_pkt_bufid_wr_p5        (    ),//(w_bufid_wr_pcb2nip [5 ]     ),
.i_pkt_bufid_ack_p5        (1'b0),//(w_bufid_ack_nip2pcb[5 ]     ),
                                                  
.   ov_pkt_bufid_p6        (    ),//(wv_bufid_pcb2nip   [6 *9+:9]),
. o_pkt_bufid_wr_p6        (    ),//(w_bufid_wr_pcb2nip [6 ]     ),
.i_pkt_bufid_ack_p6        (1'b0),//(w_bufid_ack_nip2pcb[6 ]     ),
                                                  
.   ov_pkt_bufid_p7        (    ),//(wv_bufid_pcb2nip   [7 *9+:9]),
. o_pkt_bufid_wr_p7        (    ),//(w_bufid_wr_pcb2nip [7 ]     ),
.i_pkt_bufid_ack_p7        (1'b0),//(w_bufid_ack_nip2pcb[7 ]     ),
                                                  
.   ov_pkt_bufid_p8        (    ),//(wv_bufid_pcb2nip   [8 *9+:9]),
. o_pkt_bufid_wr_p8        (    ),//(w_bufid_wr_pcb2nip [8 ]     ),
.i_pkt_bufid_ack_p8        (1'b0),//(w_bufid_ack_nip2pcb[8 ]     ),
                                                  
.   ov_pkt_bufid_p9        (    ),//(wv_bufid_pcb2nip   [9 *9+:9]),
. o_pkt_bufid_wr_p9        (    ),//(w_bufid_wr_pcb2nip [9 ]     ),
.i_pkt_bufid_ack_p9        (1'b0),//(w_bufid_ack_nip2pcb[9 ]     ),
//                                                  
//.   ov_pkt_bufid_p10       (wv_bufid_pcb2nip   [10*9+:9]),
//. o_pkt_bufid_wr_p10       (w_bufid_wr_pcb2nip [10]     ),
//.i_pkt_bufid_ack_p10       (w_bufid_ack_nip2pcb[10]     ),
//                                                  
//.   ov_pkt_bufid_p11       (wv_bufid_pcb2nip   [11*9+:9]),
//. o_pkt_bufid_wr_p11       (w_bufid_wr_pcb2nip [11]     ),
//.i_pkt_bufid_ack_p11       (w_bufid_ack_nip2pcb[11]     ),
//                                                  
//.   ov_pkt_bufid_p12       (wv_bufid_pcb2nip   [12*9+:9]),
//. o_pkt_bufid_wr_p12       (w_bufid_wr_pcb2nip [12]     ),
//.i_pkt_bufid_ack_p12       (w_bufid_ack_nip2pcb[12]     ),
//                                                  
//.   ov_pkt_bufid_p13       (wv_bufid_pcb2nip   [13*9+:9]),
//. o_pkt_bufid_wr_p13       (w_bufid_wr_pcb2nip [13]     ),
//.i_pkt_bufid_ack_p13       (w_bufid_ack_nip2pcb[13]     ),
//                                                  
//.   ov_pkt_bufid_p14       (wv_bufid_pcb2nip   [14*9+:9]),
//. o_pkt_bufid_wr_p14       (w_bufid_wr_pcb2nip [14]     ),
//.i_pkt_bufid_ack_p14       (w_bufid_ack_nip2pcb[14]     ),
//                                                  
//.   ov_pkt_bufid_p15       (wv_bufid_pcb2nip   [15*9+:9]),
//. o_pkt_bufid_wr_p15       (w_bufid_wr_pcb2nip [15]     ),
//.i_pkt_bufid_ack_p15       (w_bufid_ack_nip2pcb[15]     ),
//                                                  
//.   ov_pkt_bufid_p16       (wv_bufid_pcb2nip   [16*9+:9]),
//. o_pkt_bufid_wr_p16       (w_bufid_wr_pcb2nip [16]     ),
//.i_pkt_bufid_ack_p16       (w_bufid_ack_nip2pcb[16]     ),
//                                                  
//.   ov_pkt_bufid_p17       (wv_bufid_pcb2nip   [17*9+:9]),
//. o_pkt_bufid_wr_p17       (w_bufid_wr_pcb2nip [17]     ),
//.i_pkt_bufid_ack_p17       (w_bufid_ack_nip2pcb[17]     ),
//                                                  
//.   ov_pkt_bufid_p18       (wv_bufid_pcb2nip   [18*9+:9]),
//. o_pkt_bufid_wr_p18       (w_bufid_wr_pcb2nip [18]     ),
//.i_pkt_bufid_ack_p18       (w_bufid_ack_nip2pcb[18]     ),
//                                                  
//.   ov_pkt_bufid_p19       (wv_bufid_pcb2nip   [19*9+:9]),
//. o_pkt_bufid_wr_p19       (w_bufid_wr_pcb2nip [19]     ),
//.i_pkt_bufid_ack_p19       (w_bufid_ack_nip2pcb[19]     ),
//                                                   
//.   ov_pkt_bufid_p20       (wv_bufid_pcb2nip   [20*9+:9]),
//. o_pkt_bufid_wr_p20       (w_bufid_wr_pcb2nip [20]     ),
//.i_pkt_bufid_ack_p20       (w_bufid_ack_nip2pcb[20]     ),
//                             
//.ov_pkt_bufid_p21         (),
//.o_pkt_bufid_wr_p21       (),
//.i_pkt_bufid_ack_p21      (1'b0),

///
.i_pkt_bufid_wr_sfc      (w_pkt_bufid_wr_flt2pcb),
.iv_pkt_bufid_sfc        (wv_pkt_bufid_flt2pcb),
.iv_pkt_bufid_cnt_sfc    (wv_pkt_bufid_cnt_flt2pcb),

///
.iv_pkt_bufid_p0         (wv_pkt_bufid_nop2pcb   [0*9+:9]),
.i_pkt_bufid_wr_p0       (w_pkt_bufid_wr_nop2pcb [0]     ),
.o_pkt_bufid_ack_p0      (w_pkt_bufid_ack_pcb2nop[0]     ),

.   iv_pkt_bufid_p1      (wv_pkt_bufid_nop2pcb   [1*9+:9]),
. i_pkt_bufid_wr_p1      (w_pkt_bufid_wr_nop2pcb [1]     ),
.o_pkt_bufid_ack_p1      (w_pkt_bufid_ack_pcb2nop[1]     ),

.   iv_pkt_bufid_p2      (wv_pkt_bufid_nop2pcb   [2*9+:9]),
. i_pkt_bufid_wr_p2      (w_pkt_bufid_wr_nop2pcb [2]     ),
.o_pkt_bufid_ack_p2      (w_pkt_bufid_ack_pcb2nop[2]     ),
                                                  
.   iv_pkt_bufid_p3      (wv_pkt_bufid_nop2pcb   [3*9+:9]),
. i_pkt_bufid_wr_p3      (w_pkt_bufid_wr_nop2pcb [3]     ),
.o_pkt_bufid_ack_p3      (w_pkt_bufid_ack_pcb2nop[3]     ),
                                                  
.   iv_pkt_bufid_p4      (wv_pkt_bufid_nop2pcb   [4*9+:9]),
. i_pkt_bufid_wr_p4      (w_pkt_bufid_wr_nop2pcb [4]     ),
.o_pkt_bufid_ack_p4      (w_pkt_bufid_ack_pcb2nop[4]     ),
                                                  
.   iv_pkt_bufid_p5      (0   ),//(wv_pkt_bufid_nop2pcb   [5*9+:9]),
. i_pkt_bufid_wr_p5      (0   ),//(w_pkt_bufid_wr_nop2pcb [5]     ),
.o_pkt_bufid_ack_p5      (    ),//(w_pkt_bufid_ack_pcb2nop[5]     ),

.   iv_pkt_bufid_p6      (0   ),//(wv_pkt_bufid_nop2pcb   [6*9+:9]),
. i_pkt_bufid_wr_p6      (0   ),//(w_pkt_bufid_wr_nop2pcb [6]     ),
.o_pkt_bufid_ack_p6      (    ),//(w_pkt_bufid_ack_pcb2nop[6]     ),

.   iv_pkt_bufid_p7      (0   ),//(wv_pkt_bufid_nop2pcb   [7*9+:9]),
. i_pkt_bufid_wr_p7      (0   ),//(w_pkt_bufid_wr_nop2pcb [7]     ),
.o_pkt_bufid_ack_p7      (    ),//(w_pkt_bufid_ack_pcb2nop[7]     ),

.   iv_pkt_bufid_p8      (0   ),//(wv_pkt_bufid_nop2pcb   [8*9+:9]),
. i_pkt_bufid_wr_p8      (0   ),//(w_pkt_bufid_wr_nop2pcb [8]     ),
.o_pkt_bufid_ack_p8      (    ),//(w_pkt_bufid_ack_pcb2nop[8]     ),

.iv_pkt_bufid_p9        (wv_bufid_idc2pcb   ),
.i_pkt_bufid_wr_p9      (w_bufid_wr_idc2pcb ),
.o_pkt_bufid_ack_p9     (w_bufid_ack_pcb2idc),
//.   iv_pkt_bufid_p9      (wv_pkt_bufid_nop2pcb   [9*9+:9]),
//. i_pkt_bufid_wr_p9      (w_pkt_bufid_wr_nop2pcb [9]     ),
//.o_pkt_bufid_ack_p9      (w_pkt_bufid_ack_pcb2nop[9]     ),
//
//.   iv_pkt_bufid_p10     (wv_pkt_bufid_nop2pcb   [10*9+:9]),
//. i_pkt_bufid_wr_p10     (w_pkt_bufid_wr_nop2pcb [10]     ),
//.o_pkt_bufid_ack_p10     (w_pkt_bufid_ack_pcb2nop[10]     ),
//
//.   iv_pkt_bufid_p11     (wv_pkt_bufid_nop2pcb   [11*9+:9]),
//. i_pkt_bufid_wr_p11     (w_pkt_bufid_wr_nop2pcb [11]     ),
//.o_pkt_bufid_ack_p11     (w_pkt_bufid_ack_pcb2nop[11]     ),
//
//.   iv_pkt_bufid_p12     (wv_pkt_bufid_nop2pcb   [12*9+:9]),
//. i_pkt_bufid_wr_p12     (w_pkt_bufid_wr_nop2pcb [12]     ),
//.o_pkt_bufid_ack_p12     (w_pkt_bufid_ack_pcb2nop[12]     ),
//
//.   iv_pkt_bufid_p13     (wv_pkt_bufid_nop2pcb   [13*9+:9]),
//. i_pkt_bufid_wr_p13     (w_pkt_bufid_wr_nop2pcb [13]     ),
//.o_pkt_bufid_ack_p13     (w_pkt_bufid_ack_pcb2nop[13]     ),
//
//.   iv_pkt_bufid_p14     (wv_pkt_bufid_nop2pcb   [14*9+:9]),
//. i_pkt_bufid_wr_p14     (w_pkt_bufid_wr_nop2pcb [14]     ),
//.o_pkt_bufid_ack_p14     (w_pkt_bufid_ack_pcb2nop[14]     ),
//
//.   iv_pkt_bufid_p15     (wv_pkt_bufid_nop2pcb   [15*9+:9]),
//. i_pkt_bufid_wr_p15     (w_pkt_bufid_wr_nop2pcb [15]     ),
//.o_pkt_bufid_ack_p15     (w_pkt_bufid_ack_pcb2nop[15]     ),
//
//.   iv_pkt_bufid_p16     (wv_pkt_bufid_nop2pcb   [16*9+:9]),
//. i_pkt_bufid_wr_p16     (w_pkt_bufid_wr_nop2pcb [16]     ),
//.o_pkt_bufid_ack_p16     (w_pkt_bufid_ack_pcb2nop[16]     ),
//
//.   iv_pkt_bufid_p17     (wv_pkt_bufid_nop2pcb   [17*9+:9]),
//. i_pkt_bufid_wr_p17     (w_pkt_bufid_wr_nop2pcb [17]     ),
//.o_pkt_bufid_ack_p17     (w_pkt_bufid_ack_pcb2nop[17]     ),
//
//.   iv_pkt_bufid_p18     (wv_pkt_bufid_nop2pcb   [18*9+:9]),
//. i_pkt_bufid_wr_p18     (w_pkt_bufid_wr_nop2pcb [18]     ),
//.o_pkt_bufid_ack_p18     (w_pkt_bufid_ack_pcb2nop[18]     ),
//
//.   iv_pkt_bufid_p19     (wv_pkt_bufid_nop2pcb   [19*9+:9]),
//. i_pkt_bufid_wr_p19     (w_pkt_bufid_wr_nop2pcb [19]     ),
//.o_pkt_bufid_ack_p19     (w_pkt_bufid_ack_pcb2nop[19]     ),
//
//.   iv_pkt_bufid_p20     (wv_pkt_bufid_nop2pcb   [20*9+:9]),
//. i_pkt_bufid_wr_p20     (w_pkt_bufid_wr_nop2pcb [20]     ),
//.o_pkt_bufid_ack_p20     (w_pkt_bufid_ack_pcb2nop[20]     ),

//.iv_pkt_bufid_p21        (wv_bufid_idc2pcb   ),
//.i_pkt_bufid_wr_p21      (w_bufid_wr_idc2pcb ),
//.o_pkt_bufid_ack_p21     (w_bufid_ack_pcb2idc),
       
.ov_free_bufid_num(wv_free_buf_fifo_rdusedw_pcb2cpa)        
);

 
stream_filter_and_policing 
#(
  .clk_period(CLK125MHz_PERIOD)
)   
stream_filter_and_policing_inst
(       
        .i_clk                           (i_clk  ),  
        .i_rst_n                         (i_rst_n),
       
        .iv_addr                         (wv_addr_mih2other   ),         
        .iv_wdata                        (wv_wdata_mih2other  ),         
        .i_wr_trl                        (w_wr_cit2trl      ),      
        .i_rd_trl                        (w_rd_cit2trl      ),                                    
        .o_wr_trl                        (w_wr_trl2cit      ),      
        .ov_addr_trl                     (wv_addr_trl2cit   ),      
        .ov_rdata_trl                    (wv_rdata_trl2cit  ),
    
        .i_wr_rwc                        (w_wr_cit2idc     ),      
        .i_rd_rwc                        (w_rd_cit2idc     ),                                    
        .o_wr_rwc                        (w_wr_idc2cit     ),      
        .ov_addr_rwc                     (wv_addr_idc2cit  ),      
        .ov_rdata_rwc                    (wv_rdata_idc2cit ),
   
        .i_st_rxenable                   (i_st_rxenable                ),                                   
        .i_cyclestart                    (i_cyclestart                )   ,
        .iv_time_slot_length             (wv_time_slot_length_grm2other),
        .iv_schedule_period              (ov_schedule_period ),
  
        .iv_desp                         (wv_descriptor  ),
        .i_desp_wr                       (w_descriptor_wr),      
        
        .ov_pkt_bufid                    (wv_pkt_bufid_idc2nos),
        . ov_priority                    (wv_priority_idc2nos ),
        //.   ov_flowid                    (wv_flowid_idc       ), // float
        .   o_desp_wr                    (w_desp_wr_idc2nos   ),

   
        .ov_pkt_bufid_hcp                (wv_pkt_bufid_idc2cbo   ), 
        .ov_priority_hcp                 (wv_priority_idc2cbo    ), 
        .ov_inport_hcp                   (wv_inport_idc2cbo      ), 
        .o_desp_wr_hcp                   (w_desp_wr_idc2cbo      ), 
       
        .ov_bufid                     (wv_bufid_idc2pcb   ),
        .o_bufid_wr                   (w_bufid_wr_idc2pcb ),
        .i_bufid_ack                  (w_bufid_ack_pcb2idc)
      
);              


hcp_buffer_output hcp_buffer_output_inst(
.i_clk                  (i_clk                        ),
.i_rst_n                (i_rst_n                      ),

.iv_pkt_bufid_ctrl      (wv_pkt_bufid_idc2cbo   ),          
.iv_pkt_type_ctrl       (wv_priority_idc2cbo    ),         
.i_mac_entry_hit_ctrl   (1'b0                   ),                
.iv_pkt_inport_ctrl     (wv_inport_idc2cbo      ),         
.i_pkt_bufid_wr_ctrl    (w_desp_wr_idc2cbo      ),        
                        
.ov_pkt_bufid           (wv_pkt_bufid_nop2pcb   [INDEX_HCP*9+:9]),
.o_pkt_bufid_wr         (w_pkt_bufid_wr_nop2pcb [INDEX_HCP]     ),
.i_pkt_bufid_ack        (w_pkt_bufid_ack_pcb2nop[INDEX_HCP]     ),
                        
.ov_pkt_raddr           (wv_pkt_raddr_nop2pcb   [INDEX_HCP*16+:16]),
.o_pkt_rd               (w_pkt_rd_nop2pcb       [INDEX_HCP]),
.i_pkt_raddr_ack        (w_pkt_raddr_ack_pcb2nop[INDEX_HCP]),
                        
.iv_pkt_data            (wv_pkt_data_pcb2nop    [INDEX_HCP*SBM_PKT_WIDTH+:SBM_PKT_WIDTH]),
.i_pkt_data_wr          (w_pkt_data_wr_pcb2nop  [INDEX_HCP]),           
                        
.ov_hcp_data            (ov_data_hcp ),
.o_hcp_data_wr          (o_data_wr_hcp)
);

management_interface_hub management_interface_hub_inst(
.i_clk                            (i_clk              ),
.i_rst_n                          (i_rst_n            ),
                                                      
.iv_command                       (iv_command         ), 
.i_command_wr                     (i_command_wr       ),          
                                                      
.ov_addr                          (wv_addr_mih2other  ),
.ov_wdata                         (wv_wdata_mih2other ),

.o_wr_ffi                      (w_wr_psc_cpe2psc),
.o_rd_ffi                      (w_rd_psc_cpe2psc),
.o_wr_dex                      (w_wr_pdg_cpe2pdg),
.o_rd_dex                      (w_rd_pdg_cpe2pdg),
.o_wr_ctx                      (w_wr_ctx_cpe2ctx),
.o_rd_ctx                      (w_rd_ctx_cpe2ctx),
            
.o_wr_flt                         (w_wr_cit2flt                        ),
.o_rd_flt                         (w_rd_cit2flt                        ),
                                                                       
.o_wr_pcb                         (w_wr_cit2pcb                        ),
.o_rd_pcb                         (w_rd_cit2pcb                        ),

.o_wr_trl                         (w_wr_cit2trl                        ),
.o_rd_trl                         (w_rd_cit2trl                        ),

.o_wr_idc                         (w_wr_cit2idc                        ),
.o_rd_idc                         (w_rd_cit2idc                        ),

.o_wr_ist                         (w_wr_cit2ist                        ),
.o_rd_ist                         (w_rd_cit2ist                        ),
                                                                       
.o_wr_qgc                        (w_wr_cit2qgc                       ),
.o_rd_qgc                        (w_rd_cit2qgc                       ),
                                                                       
.o_wr_mac  (w_wr_mih2mac  ),
.o_rd_mac  (w_rd_mih2mac  ), 
               
.o_wr_tau     (w_wr_mih2tau     ),
.o_rd_tau     (w_rd_mih2tau     ),   

.i_wr_ffi                       (w_wr_psc_psc2cpe                 ),
.iv_addr_ffi                    (wv_addr_psc_psc2cpe              ),
.iv_rdata_ffi                   (wv_rdata_psc_psc2cpe             ),
                                                  
.i_wr_dex                       (w_wr_pdg_pdg2cpe                 ),
.iv_addr_dex                    (wv_addr_pdg_pdg2cpe              ),
.iv_rdata_dex                   (wv_rdata_pdg_pdg2cpe             ),
                                                  
.i_wr_ctx                       (w_wr_ctx_ctx2cpe                 ),
.iv_addr_ctx                    (wv_addr_ctx_ctx2cpe              ),
.iv_rdata_ctx                   (wv_rdata_ctx_ctx2cpe             ),
                                                                       
.i_wr_pcb                         (w_wr_pcb2cit          ),
.iv_addr_pcb                      (wv_addr_pcb2cit       ),
.iv_rdata_pcb                     (wv_rdata_pcb2cit      ), 
                                                         
.i_wr_flt                         (w_wr_flt2cit          ),
.iv_addr_flt                      (wv_addr_flt2cit       ),
.iv_rdata_flt                     (wv_rdata_flt2cit      ),

.i_wr_trl                         (w_wr_trl2cit          ),
.iv_addr_trl                      (wv_addr_trl2cit       ),
.iv_rdata_trl                     (wv_rdata_trl2cit      ),

.i_wr_idc                         (w_wr_idc2cit          ),
.iv_addr_idc                      (wv_addr_idc2cit       ),
.iv_rdata_idc                     (wv_rdata_idc2cit      ),

.i_wr_ist                         (w_wr_ist2cit          ),
.iv_addr_ist                      (wv_addr_ist2cit       ),
.iv_rdata_ist                     (wv_rdata_ist2cit      ),
                                                    
.i_wr_qgc                        (w_wr_qgc2cit         ),
.iv_addr_qgc                     (wv_addr_qgc2cit      ),
.iv_rdata_qgc                    (wv_rdata_qgc2cit     ),
                                 
.i_wr_mac                                (w_wr_mac2mih      ),
.iv_addr_mac                             (wv_addr_mac2mih   ),
.iv_rdata_mac                            (wv_rdata_mac2mih  ),  
                                             
.i_wr_tau                                   (w_wr_tau2mih        ),
.iv_addr_tau                                (wv_addr_tau2mih     ),
.iv_rdata_tau                               (wv_rdata_tau2mih    ),
                                                         
.ov_command_ack                   (ov_command_ack        ),
.o_command_ack_wr                 (o_command_ack_wr      ),

.ov_tss_ver                       (ov_tss_ver                            ),
.ov_hpriority_be_police_threshold (wv_hpriority_be_police_threshold       ), 
.ov_rc_police_threshold           (wv_rc_police_threshold_grm2nip         ),
.ov_lpriority_be_police_threshold (wv_lpriority_be_police_threshold),
.o_qbv_or_qch                     (w_qbv_or_qch_grm2nop                  ),          
.ov_time_slot_length              (wv_time_slot_length_grm2other                   ),   
.ov_schedule_period               (ov_schedule_period                    )          
);


//testaux testaux_inst(   
//    .i_clk                  (i_clk),
//    .i_rst_n                (i_rst_n),
//
//    .iv_addr                (wv_addr_mih2other    ),
//    .iv_wdata               (wv_wdata_mih2other     ),
//    .i_wr                   (w_wr_mih2tau         ),
//    .i_rd                   (w_rd_mih2tau         ),                     
//    .o_wr                   (w_wr_tau2mih         ),
//    .ov_addr                (wv_addr_tau2mih      ),
//    .ov_rdata               (wv_rdata_tau2mih     ), 
//    //gmii interfaces from p0
//    .i_gmii_rxclk_p0        (i_gmii_rxclk_p0),
//    .i_gmii_dv_p0           (i_gmii_rx_dv_p0),
//    .iv_gmii_rxd_p0         (iv_gmii_rxd_p0),
//    .i_gmii_rx_er_p0        (i_gmii_rx_er_p0),  
//    
//    .i_gmii_txclk_p0        (o_gmii_txclk_p0),        
//    .i_gmii_en_p0           (o_gmii_tx_en_p0 ),       
//    .iv_gmii_txd_p0         (ov_gmii_txd_p0  ),       
//    .i_gmii_tx_er_p0        (o_gmii_tx_er_p0 ),       
//                                                    
//    //gmii interfaces from p1                       
//    .i_gmii_rxclk_p1        (i_gmii_rxclk_p1),      
//    .i_gmii_dv_p1           (i_gmii_rx_dv_p1),         
//    .iv_gmii_rxd_p1         (iv_gmii_rxd_p1),       
//    .i_gmii_rx_er_p1        (i_gmii_rx_er_p1),      
//                                                    
//    .i_gmii_txclk_p1        (o_gmii_txclk_p1),     
//    .i_gmii_en_p1           (o_gmii_tx_en_p1 ),   
//    .iv_gmii_txd_p1         (ov_gmii_txd_p1  ),      
//    .i_gmii_tx_er_p1        (o_gmii_tx_er_p1 ),      
//                                                    
//    //gmii interfaces from p2                       
//    .i_gmii_rxclk_p2        (i_gmii_rxclk_p2),      
//    .i_gmii_dv_p2           (i_gmii_rx_dv_p2),         
//    .iv_gmii_rxd_p2         (iv_gmii_rxd_p2),
//    .i_gmii_rx_er_p2        (i_gmii_rx_er_p2),  
//    
//    .i_gmii_txclk_p2        (o_gmii_txclk_p2),
//    .i_gmii_en_p2           (o_gmii_tx_en_p2),
//    .iv_gmii_txd_p2         (ov_gmii_txd_p2),
//    .i_gmii_tx_er_p2        (o_gmii_tx_er_p2),
//    
//    //gmii interfaces from p3
//    .i_gmii_rxclk_p3        (i_gmii_rxclk_p3),
//    .i_gmii_dv_p3           (i_gmii_rx_dv_p3),
//    .iv_gmii_rxd_p3         (iv_gmii_rxd_p3),
//    .i_gmii_rx_er_p3        (i_gmii_rx_er_p3),  
//    
//    .i_gmii_txclk_p3        (o_gmii_txclk_p3),
//    .i_gmii_en_p3           (o_gmii_tx_en_p3),
//    .iv_gmii_txd_p3         (ov_gmii_txd_p3),
//    .i_gmii_tx_er_p3        (o_gmii_tx_er_p3),
//    
//    .i_cyclestart           (i_cyclestart),
//    .iv_synclk              (iv_localclk   ),
//    .iv_hcp_mac             ({24'h662662,iv_hcp_mid,12'h0}),    
//    .i_table_trigger0       (1'b0),
//    .i_table_trigger1       (1'b0),
//            
//    .o_PTO0                 (o_PTO0            ),
//    .o_PTO1                 (o_PTO1            ),
//    .o_PTO2                 (o_PTO2            ),
//    .o_PTO3                 (o_PTO3            ),
//    
//    .o_mirror_pkt_wr        (o_mirror_pkt_wr    ),
//    .ov_mirror_pkt          (ov_mirror_pkt      )
//                             
//        
//);
endmodule


